Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis

The study of reliable computation using unreliable components can be extended from stand-alone components and homogeneous networks to heterogeneous circuits. Since the components in such circuits are subjected to circuit-specific aspects like reconvergence and logic masking, their error bounds are highly dependent on circuit structure and the error bounds for each circuit is unique in that way. In this work, we present a study of circuit-specific error bounds for faulttolerant computation in heterogeneous circuits. We propose an exact probabilistic error model that can compute the maximum output error over all possible input space in a circuit-specific manner and thereby provide a tighter error bound. We also provide the worst-case input vector, which has the highest probability to generate an erroneous output, and the worstcase output error probability for any given logic circuit. We model the error estimation problem as a maximum a posteriori (MAP) estimate, over the joint error probability function of the entire circuit, calculated efficiently through an intelligent search of the entire input space using probabilistic traversal of a binary join tree using Shenoy-Shafer algorithm. The experimental results clearly show that the error bounds depend on the circuit structure and the maximum output error provides a tighter bound.